C-Testable modified-Booth multipliers
نویسندگان
چکیده
In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an Nx x Ny bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.
منابع مشابه
Path Delay Fault Testable Modified Booth Multipliers
Testing of Modified Booth Multipliers (MBMs) with respect to path delay faults, is studied in this paper. Design modifications are proposed and a path selection method is suggested. The selected paths are Single Path Propagating – Hazard Free Robustly Testable (SPPHFRT) and based on their delays the delay along any other path of the MBM can be calculated. The number of the selected paths is imp...
متن کاملDesign of High-speed Modified Booth Multipliers Operating at GHz Ranges
This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers ...
متن کاملImplementing the Functional Model of High Accuracy Fixed Width Modified Booth
The sustained growth in VLSI technology is fuelled by the continued shrinking of transistor to ever smaller dimension. The benefits of miniaturization are high packing densities, high circuit speed and low power dissipation. Binary multiplier is an electronic circuit used in digital electronics such as a computer to multiply two binary numbers, which is built using a binary adder. A fixed-width...
متن کاملHigh speed Radix-4 Booth scheme in CNTFET technology for high performance parallel multipliers
A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances o...
متن کاملPower Aware Reconfigurable Multiplier for DSP Applications
DSP applications are rich in multiplication operations. Hence there is a growing need in improving the efficiency of multipliers. To improve the performance of multipliers, reconfiguration is introduced. In this paper, reconfiguration is introduced in the form of one level recursive architecture to the existing modified booth multiplier (MBM). It provides reconfigurable modes that satisfy multi...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- J. Electronic Testing
دوره 8 شماره
صفحات -
تاریخ انتشار 1996